1. Field of the Invention
The present invention relates to a fault simulation apparatus to verify the operation of a circuit having MOS transistors, and relates more particularly to a fault simulation apparatus in which circuit connection data items showing a logic circuit model equivalent to a logic circuit to be verified is constructed by a computer, and a switch level simulation of an event-driven method is carried out under excitation by an input signal applied from outside the logic circuit, thereby verifying quality of a logic circuit design, and evaluating fault coverage of a test pattern of the logic circuit.
2. Description of the Related Art
Unlike design according to an application specific IC (hereinafter abbreviated as ASIC) method, in a full-custom design method, circuit diagrams, for example, a flip-flop, a latch circuit, and a selector circuit at a gate design level or a switch design level are used. Hence, when a fault simulation is carried out according to a conventional method, a result is outputted as Possibility of Detected Fault in which a pseudo error is possibly detected.
FIG. 1 is a circuit connection diagram showing a logic circuit serving as a verification target circuit in a fault simulation operation using a conventional fault simulation apparatus (not shown). In FIG. 1, reference number 109 denotes an input terminal of SEL, 110, 111 are input terminals DATAIN.sub.-- A and DATAIN.sub.-- B, 112 is an output terminal DATAOUT, I1 is a CMOS circuit including an inverter device 113, I2 is a CMOS circuit including a transistor 114 and an NMOS transistor 115, and I3 is a CMOS circuit including a PMOS transistor 116 and an NMOS transistor 117.
FIG. 2 is a truth table showing logic functions of the NMOS transistors 115 and 117, and
FIG. 3 is a truth table showing logic functions of the PMOS transistors 114 and 116.
FIG. 4 is a table showing results of fault simulation in the circuit connection diagram of FIG. 1. In the table, a region R shows a case where no fault is generated at an output terminal of the inverter device 113, a region S is a case where a Stuck-at 1 fault (short-circuit to a power source) is generated at the output terminal of the inverter device 113, and a region T is a case where a Stuck-at 0 fault (short-circuit to the ground) is generated at the output terminal of the inverter device 113.
A description will now be given of the operation of the conventional fault simulation apparatus.
In a model of the verification target logic circuit of FIG. 1, including the NMOS transistors 115, 117, and the PMOS transistors 114, 116 whose operations are shown in the truth tables of FIGS. 2 and 3, a fault generating portion (not shown) generates the Stuck at 1 (SA1) fault at the output terminal of the inverter device 113. In this case, only the NMOS transistor 115 serving as a transmission gate of the CMOS circuit 12 is operated to output a DATAIN.sub.-- A signal NA as shown in FIG. 1 irrespective of electric characteristics (such as poor propagation of a logic 1) in logic simulation. Hence, there is a collision between a signal NB of a logic 0 sent from the DATAIN.sub.-- B through the CMOS circuit I3 and the DATAIN.sub.-- A signal NA. Since the collision between the signals results in an indefinite value X, it is uncertain whether or not a fault is detected. Consequently, a result is outputted as fault P (Possibility Detect) showing possibility of a pseudo error.
In an actual circuit, however, the NMOS transistor 115 can generally propagate a weak signal NA of a logic 1 so that the PMOS transistor 116 can propagate a strong signal NB of a logic 0, and is at a positive potential with respect to the NMOS transistor 115. Thus, since it is possible to surely detect the fault, a result is detected as a signal D (Definitely Detected Fault) when an actual device (hereinafter referred to as Tester) detection is made to the actual circuit (see FIG. 13).
The conventional fault simulation apparatus is operated in the above manner.
As is apparent from the results of fault simulation shown in FIG. 4, when the conventional fault simulation apparatus is used to generate the fault in the circuit element, and perform the fault simulation, a fault simulation detection (a fault sim. detection) results in frequent occurrence of the pseudo error. As a result, there is a problem in that the results of Tester detection are significantly different from those of actual circuit detection. Hence, there are drawbacks of low reliability of fault coverage as the result of fault simulation obtained by the operation of the conventional fault simulation apparatus, and low efficiency of debugging of the test pattern.